New and improved VGA.vhd source code (VHDL)
After much headscratching and frustration I engaged the little grey cells and contemplated the nature of the signal I was trying to generate.
VGA signalling is very simple on the face of it but the frequencies involved are often a lot higher than things like jump wires and breadboards can sensible cope with. Most of my projects so far have used relatively sedate clock rates (sub-10MHz digital stuff).
My FPGA's main clock signal is set up to be a simple 40 Megahertz 50% duty cycle signal, derived from the FPGA dev board's on-board crystal oscillator. That's all done internally in the FPGA chip of course but the output signals of the chip have to travel (in my experiment circuit) through some cheap pin headers, over a few inches of jump wire into some more headers inside the Propeller Dev board (that I'm using simply because it has a VGA socket on it!) and out to the VGA cable into the TV.
Little wonder then that I had so much trouble getting a coherent picture to show. In the end I could get a signal I'm happy with my digressing from the standard VGA timings by a tiny amount (nudging the horizontal sync to be two pixels earlier and two pixels longer). This seems to overcome the problems in the wiring (jitter and inductance I think). So now my FPGA code can generate a lovely, sharp(ish) 800x600 VGA signal that I'm quite pleased with, now that all 4 sides are correctly registered on the screen.
Multiple TVs seem to agree that it's a reasonable signal quality so I'm confident that the bodge is required because of the breadboarded state of the system. Once I get this thing properly built (if that ever happens) then I should be able to revert to the standard VGA signalling timings.
After much headscratching and frustration I engaged the little grey cells and contemplated the nature of the signal I was trying to generate.
VGA signalling is very simple on the face of it but the frequencies involved are often a lot higher than things like jump wires and breadboards can sensible cope with. Most of my projects so far have used relatively sedate clock rates (sub-10MHz digital stuff).
My FPGA's main clock signal is set up to be a simple 40 Megahertz 50% duty cycle signal, derived from the FPGA dev board's on-board crystal oscillator. That's all done internally in the FPGA chip of course but the output signals of the chip have to travel (in my experiment circuit) through some cheap pin headers, over a few inches of jump wire into some more headers inside the Propeller Dev board (that I'm using simply because it has a VGA socket on it!) and out to the VGA cable into the TV.
Little wonder then that I had so much trouble getting a coherent picture to show. In the end I could get a signal I'm happy with my digressing from the standard VGA timings by a tiny amount (nudging the horizontal sync to be two pixels earlier and two pixels longer). This seems to overcome the problems in the wiring (jitter and inductance I think). So now my FPGA code can generate a lovely, sharp(ish) 800x600 VGA signal that I'm quite pleased with, now that all 4 sides are correctly registered on the screen.
Multiple TVs seem to agree that it's a reasonable signal quality so I'm confident that the bodge is required because of the breadboarded state of the system. Once I get this thing properly built (if that ever happens) then I should be able to revert to the standard VGA signalling timings.